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Licensing & deliverables
What you get, what you may do with it, and what it costs to keep. Everything on this page applies to every core in the portfolio — there is no per-core variation in the deliverable set or the support terms.
Four models, chosen by how you will use the core
Pricing depends on the core, the configuration and the volume, and is quoted per engagement. The structure below does not vary.
Single-project licence
Use in one named product or programme, in unlimited volume, in perpetuity. The most common choice. A one-time fee with no per-unit royalty, so your unit economics are known from the outset.
| Scope | One named product or programme |
|---|---|
| Volume | Unlimited |
| Term | Perpetual |
| Royalty | None |
| Support | 12 months included |
Multi-project licence
Use across any number of products within your organisation, in perpetuity. Appropriate when a core will become part of your standard platform rather than appearing in a single design.
| Scope | Unlimited products, one legal entity |
|---|---|
| Volume | Unlimited |
| Term | Perpetual |
| Royalty | None |
| Support | 24 months included |
Evaluation licence
Time-limited access to the full RTL, reference model and testbench so you can establish integration cost and verify performance claims against your own data before committing. The fee is credited in full against a subsequent production licence.
| Scope | Internal evaluation only |
|---|---|
| Term | 90 days, extendable |
| Contents | Full RTL, model and testbench |
| Production use | Not permitted |
| Fee | Credited against a production licence |
Academic licence
For accredited institutions, for teaching and non-commercial research. Nominal fee, full deliverable set, and permission to publish results — with attribution and without redistributing the source.
| Scope | Teaching and non-commercial research |
|---|---|
| Term | Renewable annually |
| Contents | Full deliverable set |
| Publication | Permitted with attribution |
| Redistribution | Not permitted |
What is in the release archive
Identical for every core. Nothing on this list is a paid add-on.
- VHDL source Synthesisable VHDL-2008, readable and commented, clean under GHDL and commercial lint rule sets. Vendor primitives appear only in a clearly separated wrapper layer you can replace. Everything is written in VHDL: there is no Verilog or SystemVerilog anywhere in the deliverable.
- Or a closed-box core Where the source is not part of the licence, the same core is delivered as an encrypted netlist for your synthesis tool plus a protected simulation model. It integrates, simulates and closes timing the same way; what you give up is the ability to read and modify it. Everything else on this list is unchanged.
- Reference model Bit-accurate C++ (with Python bindings) or MATLAB, matching the RTL exactly in fixed point. Includes the stimulus generator and the analysis scripts that produced every performance curve in the datasheet.
- Verification environment UVM testbench with constrained-random stimulus, a functional coverage model, assertions on all interfaces and the regression script we use for sign-off. Runs on Questa, VCS, Xcelium and — for the cores where the feature set allows — GHDL. Supplied with the source licence; with a closed-box core you receive the sign-off report and the vectors instead.
- Test vectors Directed and random vector sets with expected outputs, including the corner cases that historically broke the core during development. These are the regressions, not a demonstration subset.
- Synthesis collateral Timing constraints, synthesis and implementation scripts, and reference utilisation and timing reports for each supported target so you can confirm you are getting what we got.
- Example design A complete, buildable project that instantiates the core in a realistic system context, with a simulation you can run in the first hour.
- Documentation Datasheet with the full parameter list and characterised performance; integration guide; register map; interface timing diagrams for every transaction type; and the resource and latency equations as functions of the parameters.
- Software Bare-metal C driver and a Linux reference driver where the core has a control plane, generated from the same register description as the VHDL.
Supported implementation targets
"Supported" means we have reference results on it and we will help you close timing on it. The VHDL is vendor-neutral, so other targets are usually a matter of the wrapper layer rather than the core.
| Target | Families | Notes |
|---|---|---|
AMD / Xilinx |
Versal, Zynq UltraScale+, Kintex UltraScale+, Artix-7 | Reference results published for all portfolio cores |
Altera |
Agilex 7, Agilex 5, Stratix 10, Arria 10 | Reference results published for all portfolio cores |
Lattice |
Avant, CertusPro-NX, Certus-NX | Low-power and edge configurations |
Microchip |
PolarFire, PolarFire SoC, RTG4 | Including rad-tolerant flows for the space cores |
ASIC — standard cell |
28 nm, 22 nm, 16 nm, 12 nm, 7 nm | Synopsys and Cadence flows; foundry-independent RTL |
ASIC — mature nodes |
180 nm, 110 nm, 65 nm, 55 nm, 40 nm | Common for connectivity and low-power radio SoCs |
Twelve months included, renewable
Support means access to the engineers who wrote the core, not a ticket queue staffed by people reading the same datasheet you already have. Renewal is optional; a lapsed contract does not affect your right to keep using the version you have.
- Direct engineer access Email and scheduled calls with the development team. Response within one business day; same-day for issues blocking a tape-out or a shipment.
- Maintenance releases Bug fixes and standards-tracking updates for the duration of the support term, with a written release note describing what changed and why.
- Integration assistance Design review of your instantiation, constraint review and help with timing closure on the core's paths.
- Configuration changes Re-parameterisation within the core's documented range at no additional licence cost. Changing your mind about a parameter is not a new licence.
- Defect policy A defect against the published specification is fixed at our cost, in or out of support term, for as long as the core is in the catalogue.
Before you ask
- Can we see the source first? Yes, under an evaluation licence and an NDA. We do not release VHDL before an NDA is in place, and we do not ask you to commit to a production licence before you have run it. An evaluation can also be taken as a closed-box core if that is faster to approve on your side.
- Do you charge per-unit royalties? No. All licence models are one-time fees. Royalty accounting is administrative overhead for both parties and it makes your bill of materials unpredictable.
- Can we modify the source? Under a source licence, yes: you have the VHDL and the right to modify it for your own use. Modified versions fall outside our defect policy for the modified regions — we will still help, but we cannot warrant code we did not write. A closed-box core cannot be modified; parameters still are.
- What happens if alfacores ceases trading? Source escrow is available on request for any licence, held with an independent agent and released on defined trigger events. Under a source licence it is close to a formality, since you already hold the VHDL; with a closed-box core it is the mechanism that makes the source reachable.
- Is there an export licence requirement? It depends on the core, its configuration, the destination and the end use. The radar and EW family is the most frequently affected. We assess this before releasing any material — see our export compliance policy.
- How long from order to delivery? Catalogue cores in a standard configuration are typically delivered within five business days of contract execution and any required export clearance. Non-standard configurations depend on the change; we quote the date before you order.
Ask for a quotation.
Tell us the part number, the configuration and the licence model. Quotations are issued within three business days.