SoC infrastructure

The interconnect between everything else: a configurable crossbar with width converters, clock crossings, address remapping and access protection, generated from one description so the address map in the documentation is the address map in the RTL.

• Configurable crossbar, up to 32 masters and 32 slaves
• Width conversion from 32 to 1024 bit, upsizing and downsizing
• Asynchronous clock crossing on any port, formally verified
• Address remapping with per-master address views
• Access protection per region, with a trap response on violation
• Register slices and pipelining inserted to meet a declared timing target

Key specifications

Ports	Up to 32 masters, 32 slaves
Data width	32–1024 bit per port, mixed
Outstanding	Up to 64 transactions per port, per direction
Protocols	AXI4, AXI4-Lite, AXI3 and AXI4-Stream bridges
Interfaces	AXI4 ports, AXI4-Lite for protection and statistics

Generates the register-file VHDL, the software header, the UVM register abstraction layer, the documentation and the IP-XACT description from a single source. Every AlfaRF core's control plane is built with it, which is why the register map in a datasheet always matches the delivered RTL — the two cannot drift apart because they are generated together.

• IP-XACT, YAML or SystemRDL input
• AXI4-Lite, APB and Avalon-MM bus outputs
• Generates VHDL, C header, UVM RAL, HTML docs and IP-XACT
• Field-level access policies, reset values and side effects
• Clock-domain-crossing handling for registers in other domains
• Used for the control plane of every core in the AlfaRF portfolio

Key specifications

Input formats	IP-XACT 2014, SystemRDL 2.0, YAML
Bus outputs	AXI4-Lite, APB3/APB4, Avalon-MM
Generated	VHDL, C header, UVM RAL, HTML, IP-XACT
Register count	No architectural limit
CDC	Automatic synchroniser insertion
Licensing	Included with any AlfaRF or alfacores core licence