1 Overview
The interconnect between everything else: a configurable crossbar with width converters, clock crossings, address remapping and access protection, generated from one description so the address map in the documentation is the address map in the RTL.
2 Features
- Configurable crossbar, up to 32 masters and 32 slaves
- Width conversion from 32 to 1024 bit, upsizing and downsizing
- Asynchronous clock crossing on any port, formally verified
- Address remapping with per-master address views
- Access protection per region, with a trap response on violation
- Register slices and pipelining inserted to meet a declared timing target
3 Applications
- SoC control planes and data-movement fabric
- Designs crossing many clock domains
- Teams standardising an interconnect and register discipline
- Debug and telemetry that ships inside the product
4 Specifications
Figures below are for a representative configuration. Resource, latency and throughput scale with the build-time parameters; the released datasheet gives each as a closed-form function of those parameters so you can compute the number for your own configuration.
| Ports | Up to 32 masters, 32 slaves |
|---|---|
| Data width | 32–1024 bit per port, mixed |
| Outstanding | Up to 64 transactions per port, per direction |
| Protocols | AXI4, AXI4-Lite, AXI3 and AXI4-Stream bridges |
| Interfaces | AXI4 ports, AXI4-Lite for protection and statistics |
| Product family | SoC Infrastructure |
| Availability | Production |
5 Interfaces and control
The core presents AXI4 ports, AXI4-Lite for protection and statistics. All streaming interfaces follow the AXI4-Stream handshake with full back-pressure support; the control plane is generated by ALF-CR-REGGEN, so the register map in section 5 is generated from the same source as the delivered VHDL and cannot drift from it.
The register map is delivered as an IP-XACT description alongside a C header and a UVM register abstraction layer, all generated together. Every field carries its access policy, reset value and any side effect in the generated documentation.
6 Configuration
The core is configured through a single package file of build-time parameters and an elaboration-time consistency check that fails the build — rather than failing in simulation — when a parameter combination is not supported. There is no source fork per configuration, so you stay on the mainline release and keep receiving maintenance updates.
Re-parameterisation within the documented range is covered by your licence at no additional cost. If you need a parameter outside the documented range, that is a design services conversation rather than a new licence.
7 Verification
ALF-CR-AXI is signed off against the release criteria described on the quality page: bit-exact agreement with the reference model across the regression suite, 100 % statement, branch and toggle coverage with every exclusion reviewed, formal proof of deadlock freedom and reset correctness on the control logic, and timing closure with positive slack on every supported target from the delivered constraints.
The verification environment used for that sign-off is part of the deliverable set. You can re-run it against your own configuration on your own farm.
8 Deliverables
| VHDL source | Synthesisable VHDL-2008, readable and commented, lint-clean |
|---|---|
| Closed-box alternative | Encrypted netlist or protected model, where source is not licensed |
| Reference model | Bit-accurate C++ (Python bindings) or MATLAB, with stimulus scripts |
| Verification | UVM testbench, functional coverage model, interface assertions |
| Test vectors | Directed and constrained-random sets with expected outputs |
| Synthesis | Timing constraints, build scripts and reference reports per target |
| Example design | Buildable project instantiating the core in a system context |
| Documentation | Datasheet, integration guide, register map, interface timing |
| Software | Bare-metal C driver and Linux reference driver, where applicable |
9 Licensing and ordering
ALF-CR-AXI is available under single-project, multi-project, evaluation and academic licences. All models are one-time fees with no per-unit royalty. See licensing for the full terms, or request a quotation quoting this part number.
10 Document revision history
| Revision | Date | Change |
|---|---|---|
| 0.1 | July 2026 | Initial preliminary draft |