Host interface & data movement

A complete PCI Express endpoint with the data mover built into it, rather than a controller you then have to feed. The transaction layer, the descriptor-driven DMA engine and the host drivers are developed and verified as one thing, which is why it holds the full link rate instead of the fraction of it that a generic bridge reaches. Compliance is not a configuration: every supported lane width and link rate is signed off against the base specification, including link training, error handling and power state transitions.

• Gen1 to Gen5 at x1, x2, x4, x8 and x16, with automatic rate and width negotiation
• Descriptor-driven scatter-gather DMA, up to 8 independent channels per direction
• Sustains the full link rate on both directions at the same time, including 64 B transfers
• MSI, MSI-X and legacy interrupts; up to 2048 MSI-X vectors
• Advanced Error Reporting, ECRC, poisoned TLP handling and hot reset recovery
• SR-IOV with up to 256 virtual functions, and address translation services
• Up to 6 BARs per function, 32-bit or 64-bit, with prefetchable regions
• Linux kernel driver, DPDK poll-mode path and a Windows KMDF driver, all supplied as source

Key specifications

Link rates	2.5 / 5 / 8 / 16 / 32 GT/s (Gen1–Gen5)
Lane widths	x1, x2, x4, x8, x16
Sustained throughput	Up to 55 GB/s aggregate at Gen5 x16
DMA channels	1–8 per direction, independently configurable
Max payload	128–512 bytes, negotiated
Completion latency	Under 1 µs typical for a 4 kB read
Interfaces	AXI4 and AXI4-Stream, AXI4-Lite control
Compliance	PCI-SIG base specification checklist, link training and error injection suites

Descriptor-driven data movement between the streaming datapath and system memory. Sized for radio applications, where sustained bandwidth over a wide datapath matters more than the small-transfer efficiency a general-purpose DMA optimises for. Handles the capture buffers, replay buffers and corner-turn transfers that most signal-processing systems need.

• Up to 16 independent channels, each bidirectional
• Descriptor chaining with cyclic buffer mode
• Datapath width up to 512 bits
• 2D transfer mode for corner-turn operations
• Timestamp-triggered start for scheduled capture and replay
• Per-channel bandwidth statistics and back-pressure reporting

Key specifications

Channels	1 – 16, bidirectional
Datapath	64 – 512 bits
Throughput	> 25 GB/s at 512 bits, 400 MHz
Descriptors	Chained, cyclic, 2D modes
Triggering	Software or timestamp-based
Interfaces	AXI4 memory, AXI4-Stream, AXI4-Lite
Typical FPGA	8.4 kLUT for 4 channels @ 400 MHz