1 Overview
A complete PCI Express endpoint with the data mover built into it, rather than a controller you then have to feed. The transaction layer, the descriptor-driven DMA engine and the host drivers are developed and verified as one thing, which is why it holds the full link rate instead of the fraction of it that a generic bridge reaches. Compliance is not a configuration: every supported lane width and link rate is signed off against the base specification, including link training, error handling and power state transitions.
2 Features
- Gen1 to Gen5 at x1, x2, x4, x8 and x16, with automatic rate and width negotiation
- Descriptor-driven scatter-gather DMA, up to 8 independent channels per direction
- Sustains the full link rate on both directions at the same time, including 64 B transfers
- MSI, MSI-X and legacy interrupts; up to 2048 MSI-X vectors
- Advanced Error Reporting, ECRC, poisoned TLP handling and hot reset recovery
- SR-IOV with up to 256 virtual functions, and address translation services
- Up to 6 BARs per function, 32-bit or 64-bit, with prefetchable regions
- Linux kernel driver, DPDK poll-mode path and a Windows KMDF driver, all supplied as source
3 Applications
- Accelerator cards and data acquisition boards
- Host-attached instrumentation and capture systems
- Storage and network offload engines
- Any design that has to keep a host link saturated
4 Specifications
Figures below are for a representative configuration. Resource, latency and throughput scale with the build-time parameters; the released datasheet gives each as a closed-form function of those parameters so you can compute the number for your own configuration.
| Link rates | 2.5 / 5 / 8 / 16 / 32 GT/s (Gen1–Gen5) |
|---|---|
| Lane widths | x1, x2, x4, x8, x16 |
| Sustained throughput | Up to 55 GB/s aggregate at Gen5 x16 |
| DMA channels | 1–8 per direction, independently configurable |
| Max payload | 128–512 bytes, negotiated |
| Completion latency | Under 1 µs typical for a 4 kB read |
| Interfaces | AXI4 and AXI4-Stream, AXI4-Lite control |
| Compliance | PCI-SIG base specification checklist, link training and error injection suites |
| Product family | Host Interface & Data Movement |
| Availability | Production |
5 Interfaces and control
The core presents AXI4 and AXI4-Stream, AXI4-Lite control. All streaming interfaces follow the AXI4-Stream handshake with full back-pressure support; the control plane is generated by ALF-CR-REGGEN, so the register map in section 5 is generated from the same source as the delivered VHDL and cannot drift from it.
The register map is delivered as an IP-XACT description alongside a C header and a UVM register abstraction layer, all generated together. Every field carries its access policy, reset value and any side effect in the generated documentation.
6 Configuration
The core is configured through a single package file of build-time parameters and an elaboration-time consistency check that fails the build — rather than failing in simulation — when a parameter combination is not supported. There is no source fork per configuration, so you stay on the mainline release and keep receiving maintenance updates.
Re-parameterisation within the documented range is covered by your licence at no additional cost. If you need a parameter outside the documented range, that is a design services conversation rather than a new licence.
7 Verification
ALF-CR-PCIE is signed off against the release criteria described on the quality page: bit-exact agreement with the reference model across the regression suite, 100 % statement, branch and toggle coverage with every exclusion reviewed, formal proof of deadlock freedom and reset correctness on the control logic, and timing closure with positive slack on every supported target from the delivered constraints.
The verification environment used for that sign-off is part of the deliverable set. You can re-run it against your own configuration on your own farm.
8 Deliverables
| VHDL source | Synthesisable VHDL-2008, readable and commented, lint-clean |
|---|---|
| Closed-box alternative | Encrypted netlist or protected model, where source is not licensed |
| Reference model | Bit-accurate C++ (Python bindings) or MATLAB, with stimulus scripts |
| Verification | UVM testbench, functional coverage model, interface assertions |
| Test vectors | Directed and constrained-random sets with expected outputs |
| Synthesis | Timing constraints, build scripts and reference reports per target |
| Example design | Buildable project instantiating the core in a system context |
| Documentation | Datasheet, integration guide, register map, interface timing |
| Software | Bare-metal C driver and Linux reference driver, where applicable |
9 Licensing and ordering
ALF-CR-PCIE is available under single-project, multi-project, evaluation and academic licences. All models are one-time fees with no per-unit royalty. See licensing for the full terms, or request a quotation quoting this part number.
10 Document revision history
| Revision | Date | Change |
|---|---|---|
| 0.1 | July 2026 | Initial preliminary draft |