Converter & serial interfaces

Full JESD204C link and transport layer with a JESD204B compatibility mode. Deterministic latency is supported through Subclass 1, which matters as soon as more than one converter has to stay phase-aligned — the usual situation in any phased array or MIMO transmitter. Includes the link-establishment state machine and lane alignment.

• JESD204C 64B/66B and JESD204B 8B/10B encoding
• Up to 32.75 Gbps per lane, 1 – 8 lanes per link
• Subclass 0, 1 and 2 with deterministic latency support
• Transport-layer sample mapping generated from the converter configuration
• CRC-12 and forward error correction option on the link layer
• SYSREF handling with programmable capture alignment

Key specifications

Standards	JESD204C, JESD204B backward compatible
Lane rate	Up to 32.75 Gbps
Lanes	1 – 8 per link, multiple links per instance
Subclass	0, 1, 2
Latency	Deterministic in Subclass 1, reported per build
Interfaces	AXI4-Stream, AXI4-Lite, transceiver-agnostic PHY port
Typical FPGA	11 kLUT per 4-lane link (excluding transceivers)

Capture interface for converters that use a parallel LVDS or CMOS bus rather than a serial link — still the majority of mid-rate parts. Handles per-lane deskew, bit-slip alignment against a known training pattern, and the automatic alignment sequence at power-up so the interface is not a board-bring-up problem.

• DDR and SDR capture, 1 – 32 data lanes
• Per-lane programmable input delay for deskew
• Automatic bit-slip alignment against a training pattern
• Eye-margin scan reporting for signal-integrity verification
• Optional bit-order and endianness correction
• Thin, replaceable vendor-primitive wrapper layer

Key specifications

Signalling	LVDS and CMOS, DDR or SDR
Lanes	1 – 32
Bit rate	Up to 1.6 Gbps per lane (device dependent)
Alignment	Automatic bit-slip and per-lane deskew
Diagnostics	Eye-margin scan per lane
Interfaces	AXI4-Stream data, AXI4-Lite control
Targets	FPGA (vendor I/O primitives in wrapper layer)