1 Overview
Full JESD204C link and transport layer with a JESD204B compatibility mode. Deterministic latency is supported through Subclass 1, which matters as soon as more than one converter has to stay phase-aligned — the usual situation in any phased array or MIMO transmitter. Includes the link-establishment state machine and lane alignment.
2 Features
- JESD204C 64B/66B and JESD204B 8B/10B encoding
- Up to 32.75 Gbps per lane, 1 – 8 lanes per link
- Subclass 0, 1 and 2 with deterministic latency support
- Transport-layer sample mapping generated from the converter configuration
- CRC-12 and forward error correction option on the link layer
- SYSREF handling with programmable capture alignment
3 Applications
- Data converter interfacing on any mixed-signal board
- Multi-channel acquisition with deterministic latency
- Bonded transceiver links and proprietary protocols
- Board bring-up and interface debug
4 Specifications
Figures below are for a representative configuration. Resource, latency and throughput scale with the build-time parameters; the released datasheet gives each as a closed-form function of those parameters so you can compute the number for your own configuration.
| Standards | JESD204C, JESD204B backward compatible |
|---|---|
| Lane rate | Up to 32.75 Gbps |
| Lanes | 1 – 8 per link, multiple links per instance |
| Subclass | 0, 1, 2 |
| Latency | Deterministic in Subclass 1, reported per build |
| Interfaces | AXI4-Stream, AXI4-Lite, transceiver-agnostic PHY port |
| Typical FPGA | 11 kLUT per 4-lane link (excluding transceivers) |
| Product family | Converter & Serial Interfaces |
| Availability | Production |
5 Interfaces and control
The core presents AXI4-Stream, AXI4-Lite, transceiver-agnostic PHY port. All streaming interfaces follow the AXI4-Stream handshake with full back-pressure support; the control plane is generated by ALF-CR-REGGEN, so the register map in section 5 is generated from the same source as the delivered VHDL and cannot drift from it.
The register map is delivered as an IP-XACT description alongside a C header and a UVM register abstraction layer, all generated together. Every field carries its access policy, reset value and any side effect in the generated documentation.
6 Configuration
The core is configured through a single package file of build-time parameters and an elaboration-time consistency check that fails the build — rather than failing in simulation — when a parameter combination is not supported. There is no source fork per configuration, so you stay on the mainline release and keep receiving maintenance updates.
Re-parameterisation within the documented range is covered by your licence at no additional cost. If you need a parameter outside the documented range, that is a design services conversation rather than a new licence.
7 Verification
ALF-CR-JESD204C is signed off against the release criteria described on the quality page: bit-exact agreement with the reference model across the regression suite, 100 % statement, branch and toggle coverage with every exclusion reviewed, formal proof of deadlock freedom and reset correctness on the control logic, and timing closure with positive slack on every supported target from the delivered constraints.
The verification environment used for that sign-off is part of the deliverable set. You can re-run it against your own configuration on your own farm.
8 Deliverables
| VHDL source | Synthesisable VHDL-2008, readable and commented, lint-clean |
|---|---|
| Closed-box alternative | Encrypted netlist or protected model, where source is not licensed |
| Reference model | Bit-accurate C++ (Python bindings) or MATLAB, with stimulus scripts |
| Verification | UVM testbench, functional coverage model, interface assertions |
| Test vectors | Directed and constrained-random sets with expected outputs |
| Synthesis | Timing constraints, build scripts and reference reports per target |
| Example design | Buildable project instantiating the core in a system context |
| Documentation | Datasheet, integration guide, register map, interface timing |
| Software | Bare-metal C driver and Linux reference driver, where applicable |
9 Licensing and ordering
ALF-CR-JESD204C is available under single-project, multi-project, evaluation and academic licences. All models are one-time fees with no per-unit royalty. See licensing for the full terms, or request a quotation quoting this part number.
10 Document revision history
| Revision | Date | Change |
|---|---|---|
| 0.1 | July 2026 | Initial preliminary draft |