1 Overview
Generates the register-file VHDL, the software header, the UVM register abstraction layer, the documentation and the IP-XACT description from a single source. Every AlfaRF core's control plane is built with it, which is why the register map in a datasheet always matches the delivered RTL — the two cannot drift apart because they are generated together.
2 Features
- IP-XACT, YAML or SystemRDL input
- AXI4-Lite, APB and Avalon-MM bus outputs
- Generates VHDL, C header, UVM RAL, HTML docs and IP-XACT
- Field-level access policies, reset values and side effects
- Clock-domain-crossing handling for registers in other domains
- Used for the control plane of every core in the AlfaRF portfolio
3 Applications
- SoC control planes and data-movement fabric
- Designs crossing many clock domains
- Teams standardising an interconnect and register discipline
- Debug and telemetry that ships inside the product
4 Specifications
Figures below are for a representative configuration. Resource, latency and throughput scale with the build-time parameters; the released datasheet gives each as a closed-form function of those parameters so you can compute the number for your own configuration.
| Input formats | IP-XACT 2014, SystemRDL 2.0, YAML |
|---|---|
| Bus outputs | AXI4-Lite, APB3/APB4, Avalon-MM |
| Generated | VHDL, C header, UVM RAL, HTML, IP-XACT |
| Register count | No architectural limit |
| CDC | Automatic synchroniser insertion |
| Licensing | Included with any AlfaRF or alfacores core licence |
| Product family | SoC Infrastructure |
| Availability | Production |
5 Interfaces and control
Interface details are configuration-dependent and are given in the released datasheet.
The register map is delivered as an IP-XACT description alongside a C header and a UVM register abstraction layer, all generated together. Every field carries its access policy, reset value and any side effect in the generated documentation.
6 Configuration
The core is configured through a single package file of build-time parameters and an elaboration-time consistency check that fails the build — rather than failing in simulation — when a parameter combination is not supported. There is no source fork per configuration, so you stay on the mainline release and keep receiving maintenance updates.
Re-parameterisation within the documented range is covered by your licence at no additional cost. If you need a parameter outside the documented range, that is a design services conversation rather than a new licence.
7 Verification
ALF-CR-REGGEN is signed off against the release criteria described on the quality page: bit-exact agreement with the reference model across the regression suite, 100 % statement, branch and toggle coverage with every exclusion reviewed, formal proof of deadlock freedom and reset correctness on the control logic, and timing closure with positive slack on every supported target from the delivered constraints.
The verification environment used for that sign-off is part of the deliverable set. You can re-run it against your own configuration on your own farm.
8 Deliverables
| VHDL source | Synthesisable VHDL-2008, readable and commented, lint-clean |
|---|---|
| Closed-box alternative | Encrypted netlist or protected model, where source is not licensed |
| Reference model | Bit-accurate C++ (Python bindings) or MATLAB, with stimulus scripts |
| Verification | UVM testbench, functional coverage model, interface assertions |
| Test vectors | Directed and constrained-random sets with expected outputs |
| Synthesis | Timing constraints, build scripts and reference reports per target |
| Example design | Buildable project instantiating the core in a system context |
| Documentation | Datasheet, integration guide, register map, interface timing |
| Software | Bare-metal C driver and Linux reference driver, where applicable |
9 Licensing and ordering
ALF-CR-REGGEN is available under single-project, multi-project, evaluation and academic licences. All models are one-time fees with no per-unit royalty. See licensing for the full terms, or request a quotation quoting this part number.
10 Document revision history
| Revision | Date | Change |
|---|---|---|
| 0.1 | July 2026 | Initial preliminary draft |