Everything around the datapath, at full link rate.
alfacores licenses the infrastructure an FPGA or ASIC needs before it can do anything useful: the host link, the data movers, the converter interfaces, the network and the fabric between them. Same RTL discipline and the same deliverable set as our sister company AlfaRF — applied to the board rather than the radio.
- Gen5
- PCI Express to x16, compliant at the full link rate
- 7
- Licensable cores across four product families
- < 4 wk
- Typical evaluation-to-integration cycle
- 100%
- Statement, branch and toggle coverage sign-off
PCI Express, compliant and saturated
Most PCIe problems are not link problems. The link trains, the board enumerates, and then the design moves a fraction of the bandwidth it paid for because the data mover was bolted on afterwards. ALF-CR-PCIE is one core: transaction layer, DMA engine and host drivers developed and signed off together, at every supported lane width and link rate.
| Link rates | 2.5 / 5 / 8 / 16 / 32 GT/s (Gen1–Gen5) |
|---|---|
| Lane widths | x1, x2, x4, x8, x16 |
| Sustained throughput | Up to 55 GB/s aggregate at Gen5 x16 |
| DMA channels | 1–8 per direction, independently configurable |
| Virtualisation | SR-IOV with up to 256 virtual functions |
| Interrupts | MSI, MSI-X to 2048 vectors, legacy |
| Interfaces | AXI4 and AXI4-Stream, AXI4-Lite control |
| Software | Linux, DPDK and Windows drivers, source included |
Three things follow from building it as one core rather than a controller and a data mover that meet at integration:
- Compliance is not a configuration. Link training, error handling and reporting, power state transitions and hot reset recovery are signed off at every supported width and rate.
- The full rate, both directions at once — including at 64-byte transfers, where a generic bridge collapses to a fraction of the link.
- Drivers are part of the core. Linux, DPDK and Windows, as source, versioned with the RTL and driving a register map generated from the same description as the hardware.
Four families that cover the board around the datapath
Every core ships as portable, vendor-neutral VHDL — or as a closed box, on the same deliverable set — with the same coding conventions and the same register map generator, so blocks from different families, and from AlfaRF, integrate without an adapter layer.
Host Interface & Data Movement
Getting data between a host, external memory and the datapath without losing the link rate on the way.
- PCI Express Gen1–Gen5 endpoint with DMA
- Multi-channel scatter-gather DMA
- Full link rate in both directions at once
- Host drivers delivered as source
Converter & Serial Interfaces
The link between the analogue edge of the board and the logic that processes it.
- JESD204B/C transmit and receive
- LVDS and CMOS converter interfaces
- Per-lane deskew and automatic bit-slip alignment
- Deterministic latency across resets
Networking
Line-rate transport with no processor in the path, from 10G to 100G.
- 10G, 25G, 40G, 50G and 100G Ethernet MAC
- Hardware UDP/IP offload, 64 flows
- Line rate at any frame size, both directions
- Optional IEEE 1588 timestamping
SoC Infrastructure
The fabric, the control plane and the instrumentation that hold a design together.
- AXI4 crossbar up to 32 masters and 32 slaves
- Width, clock and protection conversion
- Register map generation from one description
- Generated C headers, UVM RAL and IP-XACT
Two products above core level
Both are built on the cores above, so the behaviour is specified rather than discovered — an evaluation kit line for putting an interface on a bench, and a finished PCI Express to HDMI rendering product.
EVKits
Small FMC modules that bring one interface out to real connectors and attach to a carrier you already own. The line starts with the MIPI FMC EVK: four MIPI ports on one module, reference design in the box.
PCIe Graphic Renderer
Data in over PCI Express, rendered in 2D and driven out over HDMI — no host GPU and no host in the display path, so the latency is a published number rather than a distribution.
AlfaRF does the radio
Wireless and satellite modems, the digital front-end around them, and the channel coding underneath. If your problem is what happens to the signal rather than how it gets on and off the board, that is the catalogue you want.
| Modems | DVB-S2X, 5G NR, QAM, PSK, CPM, CCSDS, OFDM |
|---|---|
| Digital front-end | Pre-distortion, DUC/DDC, fractional resampling |
| Channel coding | LDPC encoding and decoding, Viterbi |
Tell us what the link has to carry.
Sustained bandwidth, transfer size, latency budget, host operating system. We will tell you which core fits, what it costs in logic, and where it does not fit.