1 Overview
A MAC and a hardware UDP/IP stack, so a data source can put packets on the wire at line rate without a processor in the path. Checksums, fragmentation, ARP and ICMP are handled in logic; the application sees a stream socket per flow.
2 Features
- 10G, 25G, 40G, 50G and 100G, with 1G fallback for management
- Hardware UDP/IPv4 and IPv6 with checksum generation and verification
- Up to 64 concurrent flows, each with its own AXI4-Stream port
- ARP, ICMP echo and IGMP handled in logic, with a host override path
- Jumbo frames to 9600 bytes; RFC 2544 line rate at 64-byte frames
- Optional IEEE 1588 timestamp insertion on ingress and egress
3 Applications
- Line-rate data streaming without a processor in the path
- Capture systems streaming straight to a host or a recorder
- Offload engines that keep the processor out of the datapath
- Instruments distributing data across a network
4 Specifications
Figures below are for a representative configuration. Resource, latency and throughput scale with the build-time parameters; the released datasheet gives each as a closed-form function of those parameters so you can compute the number for your own configuration.
| Rates | 1G / 10G / 25G / 40G / 50G / 100G |
|---|---|
| Throughput | Line rate at any frame size, both directions |
| Flows | Up to 64, independently addressed |
| Latency | Under 300 ns MAC-to-stream at 25G |
| Interfaces | AXI4-Stream per flow, AXI4-Lite control, transceiver-native line side |
| Product family | Networking |
| Availability | Production |
5 Interfaces and control
The core presents AXI4-Stream per flow, AXI4-Lite control, transceiver-native line side. All streaming interfaces follow the AXI4-Stream handshake with full back-pressure support; the control plane is generated by ALF-CR-REGGEN, so the register map in section 5 is generated from the same source as the delivered VHDL and cannot drift from it.
The register map is delivered as an IP-XACT description alongside a C header and a UVM register abstraction layer, all generated together. Every field carries its access policy, reset value and any side effect in the generated documentation.
6 Configuration
The core is configured through a single package file of build-time parameters and an elaboration-time consistency check that fails the build — rather than failing in simulation — when a parameter combination is not supported. There is no source fork per configuration, so you stay on the mainline release and keep receiving maintenance updates.
Re-parameterisation within the documented range is covered by your licence at no additional cost. If you need a parameter outside the documented range, that is a design services conversation rather than a new licence.
7 Verification
ALF-CR-ETH is signed off against the release criteria described on the quality page: bit-exact agreement with the reference model across the regression suite, 100 % statement, branch and toggle coverage with every exclusion reviewed, formal proof of deadlock freedom and reset correctness on the control logic, and timing closure with positive slack on every supported target from the delivered constraints.
The verification environment used for that sign-off is part of the deliverable set. You can re-run it against your own configuration on your own farm.
8 Deliverables
| VHDL source | Synthesisable VHDL-2008, readable and commented, lint-clean |
|---|---|
| Closed-box alternative | Encrypted netlist or protected model, where source is not licensed |
| Reference model | Bit-accurate C++ (Python bindings) or MATLAB, with stimulus scripts |
| Verification | UVM testbench, functional coverage model, interface assertions |
| Test vectors | Directed and constrained-random sets with expected outputs |
| Synthesis | Timing constraints, build scripts and reference reports per target |
| Example design | Buildable project instantiating the core in a system context |
| Documentation | Datasheet, integration guide, register map, interface timing |
| Software | Bare-metal C driver and Linux reference driver, where applicable |
9 Licensing and ordering
ALF-CR-ETH is available under single-project, multi-project, evaluation and academic licences. All models are one-time fees with no per-unit royalty. See licensing for the full terms, or request a quotation quoting this part number.
10 Document revision history
| Revision | Date | Change |
|---|---|---|
| 0.1 | July 2026 | Initial preliminary draft |